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V er s io n 2.1 , 1 2 M ay 2 00 9
CoolSET -F3
ICE3A1065ELJ
Off-Line SMPS Current Mode Controller with integrated 650V CoolMOS(R) and Startup Cell (Latched and frequency jitter Mode)
(R)
Power Management & Supply
Never
stop
thinking.
CoolSET(R)-F3 ICE3A1065ELJ Revision History: Previous Version: V2.0 Page 3, 26
2009-05-12
Datasheet
Subjects (major changes since last revision) Revise marking
For questions on technology, delivery and prices please contact the Infineon Technologies Offices in Germany or the Infineon Technologies Companies and Representatives worldwide: see our webpage at http:// www.infineon.com CoolMOS(R), CoolSET(R) are trademarks of Infineon Technologies AG.
Edition 2009-05-12 Published by Infineon Technologies AG, 81726 Munich, Germany, (c) 2008 Infineon Technologies AG. All Rights Reserved. Legal disclaimer The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights of any third party. Information For further information on technology, delivery terms and conditions and prices, please contact your nearest Infineon Technologies Office (www.infineon.com). Warnings Due to technical requirements, components may contain dangerous substances. For information on the types in question, please contact your nearest Infineon Technologies Office. Infineon Technologies Components may be used in life-support devices or systems only with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.
CoolSET(R)-F3
ICE3A1065ELJ
Off-Line SMPS Current Mode Controller with integrated 650V CoolMOS(R) and Startup Cell (Latched and frequency jitter Mode)
Product Highlights * Active Burst Mode to reach the lowest Standby Power Requirements < 100mW * Built-in latched off mode and external latch enable function to increase robustness of the system * Built-in and extendable blanking window for high load jumps to increase system reliability * Built-in soft start * Frequency jitter for low EMI * Robustness to system noise * Pb-free lead plating; RoHS compliant
PG-DIP-8 test
Features
* * * * * * * * * * * * * * * 650V avalanche rugged CoolMOS(R) with built-in Startup Cell Active Burst Mode for lowest Standby Power Fast load jump response in Active Burst Mode 100kHz internally fixed switching frequency Built-in latched Off Mode for Overtemperature, Overvoltage & Short Winding Detection Auto Restart Mode for Overload, Open Loop & VCC Undervoltage Built-in Soft Start Built-in and extendable blanking Window for short duration high current External latch enable function Max Duty Cycle 75% Overall tolerance of Current Limiting < 5% Internal PWM Leading Edge Blanking BiCMOS technology provide wide VCC range Frequency jitter and soft driving for low EMI Robustness to system noise such as ESD, lightning surge, etc.
Description
The CoolSET(R)F3 ELJ version is the enhanced LJ version for system noise. It retains all the features of LJ series such as BiCMOS technologies, active burst mode, frequency jitter, propagation delay compensation, built-in soft start, auto-restart protection for over load and open loop, latch off protection for over voltage, over temperature and short winding, external latch off enable, built-in and extendable blanking time for short period of over power, etc. It is target for low power SMPS application such as Off-Line Battery Adapters, DVD player and recorder, set-top box, auxiliary power supply, etc. The ELJ version has implemented some noise resist techniques to the IC such that it is more robust to the system noise which is generated during system ESD test, lightning surge test, transient test, etc.
Typical Application
+
85 ... 270 VAC
CBulk CVCC VCC
Snubber
Converter DC Output
-
Drain
Startup Cell
Power Management PWM Controller Current Mode Precise Low Tolerance Peak Current Limitation Active Burst Mode Latched Off Mode Auto Restart Mode Depl. CoolMOSTM
CS RSense FB BL
GND
Control Unit
CoolSET(R)-F3
( Latch & Jitter )
Type ICE3A1065ELJ
1) 2)
Package PG-DIP-8
Marking 3A1065ELJ
VDS 650V
FOSC 100kHz
RDSon1) 2.95
230VAC 15%2) 32W
85-265 VAC2) 16W
typ @ T=25C Calculated maximum input power rating at Ta=75C, Tj=125C and without copper area as heat sink.
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Table of Contents 1 1.1 1.2 2 3 3.1 3.2 3.3 3.3.1 3.3.2 3.4 3.5 3.5.1 3.5.2 3.5.3 3.6 3.6.1 3.6.2 3.7 3.7.1 3.7.2 3.7.2.1 3.7.2.2 3.7.2.3 3.7.3 3.7.3.1 3.7.3.2 4 4.1 4.2 4.3 4.3.1 4.3.2 4.3.3 4.3.4 4.3.5 4.3.6 4.3.7 5 Page
Pin Configuration and Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 Pin Configuration with PG-DIP-8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 Pin Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 Representative Blockdiagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 Improved Current Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 PWM-OP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 PWM-Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Startup Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 PWM Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 PWM-Latch FF1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Gate Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Current Limiting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Leading Edge Blanking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 Propagation Delay Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 Control Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Basic and Extendable Blanking Mode . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Active Burst Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Entering Active Burst Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Working in Active Burst Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Leaving Active Burst Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Protection Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 Latched Off Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 Auto Restart Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 Supply Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 Internal Voltage Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 PWM Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 Soft Start time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 Control Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 Current Limiting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 CoolMOS(R) Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 Temperature derating curve . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
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6 7 8
Outline Dimension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 Schematic for recommended PCB layout . . . . . . . . . . . . . . . . . . . . . . . .27
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Pin Configuration and Functionality
1
1.1
Pin Configuration and Functionality
Pin Configuration with PG-DIP-8
1.2
Pin Functionality
Pin 1 2 3 4 5 6 7 8
1)
Symbol BL FB CS Drain Drain n.c. VCC GND
Function Blanking and Latch Feedback Current Sense/ 650V1) CoolMOS(R) Source 650V1) CoolMOS(R) Drain 650V1) CoolMOS(R) Drain Not Connected Controller Supply Voltage Controller Ground
BL (Blanking and Latch) The BL pin combines the functions of extendable blanking time for entering the Auto Restart Mode and the external latch enable. The extendable blanking time function is to extend the built-in 20ms blanking time by adding an external capacitor at BL to ground. The external latch enable function is an external access to latch off the IC. It is triggered by pulling down the BL pin to less than 0.1V. FB (Feedback) The information about the regulation is provided by the FB Pin to the internal Protection Unit and to the internal PWM-Comparator to control the duty cycle. The FBSignal controls in case of light load the Active Burst Mode of the controller. CS (Current Sense) The Current Sense pin senses the voltage developed on the series resistor inserted in the source of the integrated CoolMOS(R). If CS reaches the internal threshold of the Current Limit Comparator, the Driver output is immediately switched off. Furthermore the current information is provided for the PWMComparator to realize the Current Mode.
at Tj = 110C
Package PG-DIP-8
BL
1
8
GND
Drain (Drain of integrated CoolMOS(R)) Pin Drain is the connection to the Drain of the internal CoolMOS(R). VCC (Power supply) The VCC pin is the positive supply of the IC. The operating range is between 10.5V and 26V. GND (Ground) The GND pin is the ground of the controller.
FB
2
7
VCC
CS
3
6
n.c.
Drain
4
5
Drain
Figure 1 Note:
Pin Configuration PG-DIP-8(top view) Pin 4 and 5 are shorted within the DIP 8 package.
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2
Figure 2
+ CBulk Snubber Conver DC Out VOUT CVCC
Version 2.1
VCC
Power Management Internal Bias Voltage Reference 5.0V
85 ... 270 VAC
Drain
CoolMOS(R) Startup Cell
5.0V
3.25k
IBK
BL GND
Undervoltage Lockout
18V 0.72 10.5V
T2
Latch Enable Signal #2
Power-Down Reset Oscillator
Duty Cycle max
T3
0.6V
Latched Off Mode Reset VVCC < 6.23V PWM Section
#1 CBK
Representative Blockdiagram
& G1 Soft Start Soft-Start Comparator
Clock Freq. jitter
TLE
T1
0.9V 1 G3 Latched Off Mode
VCC Spike Blanking 8.0us Thermal Shutdown
Tj >140C
24V
C1
1 ms counter Soft Start Block C7 1 G8 & G9 PWM Comparator & G5 Propagation-Delay Compensation
0.6V
0.1V 8us Blanking Time 1 G2 C8 C11 Auto Restart Mode Active Burst Mode C10 x3.2 PWM OP & G11 Current Mode & G10 C12 Spike Blanking 190ns 1.66V
C2
& G7 FF1 S RQ
Gate Driver
Representative Blockdiagram
7
20ms Blanking Time 20ms Blanking Time & G6 Spike Blanking 8.0us 10k 1pF D1 Vcsth Leading Edge Blanking 220ns 0.31V Current Limiting
S1
4.0V
C3
5.0V
RFB
4.5V
C4
25k
FB
C5
CS
RSense
2pF
1.35V
3.61V
C6a
ICE3Axx65ELJ / CoolSET(R)-F3 ( Latch & Jitter Mode )
Control Unit
3.0V
C6b
CoolSET(R)-F3 ICE3A1065ELJ
Representative Blockdiagram
# : optional external components; #1 : CBK is used to extand the Blanking Time #2 : TLE is used to enable the external Latch function
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Functional Description
3
Functional Description
the BL pin is pulled down to less than 0.1V, the Latch Off Mode is triggered. The Auto Restart Mode reduces the average power conversion to a minimum under unsafe operating conditions. This is necessary for a prolonged fault condition which could otherwise lead to a destruction of the SMPS over time. Once the malfunction is removed, normal operation is automatically retained after the next Start Up Phase. The internal precise peak current limitation reduces the costs for the transformer and the secondary diode. The influence of the change in the input voltage on the power limitation can be avoided together with the integrated Propagation Delay Compensation. Therefore the maximum power is nearly independent on the input voltage which is required for wide range SMPS. There is no need for an extra over-sizing of the SMPS, e.g. the transformer or the secondary diode. Furthermore, this ELJ version implements the frequency jitter mode to the switching clock such that the EMI noise will be effectively reduced.
All values which are used in the functional description are typical values. For calculating the worst cases the min/max values which can be found in section 4 Electrical Characteristics have to be considered.
3.1
(R)
Introduction
CoolSET -F3 ELJ series is the enhanced version of the LJ series. Not only retains all the features of LJ series but it also implements with special technique to make the IC more robust to the system noise which is generated during transient test, system ESD test, lightning surge test, etc. In order to obtain the best-in class low standby power, a new fully integrated Standby Power concept is implemented into the IC. An intelligent Active Burst Mode is used for this Standby Mode. After entering this mode there is still a full control of the power conversion by the secondary side via the same optocoupler that is used for the normal PWM control. The response on load jumps is optimized. The voltage ripple on Vout is minimized. Vout is on well controlled in this mode. The usually external connected RC-filter in the feedback line after the optocoupler is integrated in the IC to reduce the external part count. Furthermore a high voltage Startup Cell is integrated into the IC which is switched off once the Undervoltage Lockout on-threshold of 18V is exceeded. This Startup Cell is part of the integrated CoolMOS(R). The external startup resistor is no longer necessary as this Startup Cell is connected to the Drain. Power losses are therefore reduced. This increases the efficiency under light load conditions drastically. This version is adopting the BiCMOS technology and it can increase design flexibility as the Vcc voltage range is increased to 26V. For this ELJ version, the soft start is a built-in function. It is set at 20ms. Then it can save external component counts. There are 2 modes of blanking time for high load jumps; the basic mode and the extendable mode. The blanking time for the basic mode is set at 20ms while the extendable mode will increase the blanking time from basic mode by adding external capacitor at the BL pin. During this time window the overload detection is disabled. In order to increase the robustness and safety of the system, the IC provides 2 levels of protection modes: Latched Off Mode and Auto Restart Mode. The Latched Off Mode is only entered under dangerous conditions which can damage the SMPS if not switched off immediately. A restart of the system can only be done by recycling the AC line. In addition, for this ELJ version, there is an external Latch Enable function provided to increase the flexibility in protection. When
3.2
Drain
Power Management
VCC Startup Cell
CoolM OS (R)
Power M anagement Internal Bias Latched Off M ode Reset V V CC < 6.23V Power-Down Reset Undervoltage Lockout 18V 10.5V
Voltage R eference
5.0V
Auto R estart Mode
Soft Start block
Active Burst Mode Latched Off Mode
Figure 3
Power Management
The Undervoltage Lockout monitors the external supply voltage VVCC. When the SMPS is plugged to the main line the internal Startup Cell is biased and starts to charge the external capacitor CVCC which is
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Functional Description
connected to the VCC pin. This VCC charge current is controlled to 0.9mA by the Startup Cell. When the VVCC exceeds the on-threshold VCCon=18V, the bias circuit are switched on. Then the Startup Cell is switched off by the Undervoltage Lockout and therefore no power losses present due to the connection of the Startup Cell to the Drain voltage. To avoid uncontrolled ringing at switch-on a hysteresis start up voltage is implemented. The switch-off of the controller can only take place after Active Mode was entered and VVCC falls below 10.5V. The maximum current consumption before the controller is activated is about 250A. When VVCC falls below the off-threshold VCCoff=10.5V, the bias circuit switched off and the soft start counter is reset. Thus it is ensured that at every startup cycle the soft start starts at zero. The internal bias circuit is switched off if Latched Off Mode or Auto Restart Mode is entered. The current consumption is then reduced to 250A. Once the malfunction condition is removed, this block will then turn back on. The recovery from Auto Restart Mode does not require re-cycling the AC line. In case Latched Off Mode is entered, VCC needs to be lowered below 6.23V to reset the Latched Off Mode. This is done usually by re-cycling the AC line. When Active Burst Mode is entered, the internal Bias is switched off most of the time but the Voltage Reference is kept alive in order to reduce the current consumption below 450A. Current Mode means the duty cycle is controlled by the slope of the primary current. This is done by comparing the FB signal with the amplified current sense signal.
Amplified Current Signal FB 0.6V Driver t
Ton t
Figure 5 Pulse Width Modulation In case the amplified current sense signal exceeds the FB signal the on-time Ton of the driver is finished by resetting the PWM-Latch (see Figure 5). The primary current is sensed by the external series resistor RSense inserted in the source of the integrated CoolMOS(R). By means of Current Mode regulation, the secondary output voltage is insensitive to the line variations. The current waveform slope will change with the line variation, which controls the duty cycle. The external RSense allows an individual adjustment of the maximum source current of the integrated CoolMOS(R). To improve the Current Mode during light load conditions the amplified current ramp of the PWM-OP is superimposed on a voltage ramp, which is built by the switch T2, the voltage source V1 and a resistor R1 (see Figure 6). Every time the oscillator shuts down for maximum duty cycle limitation the switch T2 is closed by VOSC. When the oscillator triggers the Gate Driver, T2 is opened so that the voltage ramp can start. In case of light load the amplified current ramp is too small to ensure a stable regulation. In that case the Voltage Ramp is a well defined signal for the comparison with the FB-signal. The duty cycle is then controlled by the slope of the Voltage Ramp. By means of the time delay circuit which is triggered by the inverted VOSC signal, the Gate Driver is switched-off until it reaches approximately 156ns delay time (see Figure 7). It allows the duty cycle to be reduced continuously till 0% by decreasing VFB below that threshold.
3.3
Improved Current Mode
Soft-Start Comparator PWM-Latch C8
R Q
FB
Driver
S 0.6V Q
PWM OP x3.2 Improved Current Mode
Figure 4 Current Mode
CS
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Functional Description
3.3.1 PWM-OP
Soft-Start Comparator PWM Comparator FB Oscillator VOSC
time delay circuit (156ns)
C8 PWM-Latch
The input of the PWM-OP is applied over the internal leading edge blanking to the external sense resistor RSense connected to pin CS. RSense converts the source current into a sense voltage. The sense voltage is amplified with a gain of 3.2 by PWM OP. The output of the PWM-OP is connected to the voltage source V1. The voltage ramp with the superimposed amplified current signal is fed into the positive inputs of the PWMComparator C8 and the Soft-Start-Comparator (see Figure 6).
Gate Driver
3.3.2
PWM-Comparator
10k T2 C1 Voltage Ramp
Figure 6
0.6V X3.2 V1 PWM OP
R1
The PWM-Comparator compares the sensed current signal of the integrated CoolMOS(R) with the feedback signal VFB (see Figure 8). VFB is created by an external optocoupler or external transistor in combination with the internal pull-up resistor RFB and provides the load information of the feedback circuitry. When the amplified current signal of the integrated CoolMOS(R) exceeds the signal VFB the PWM-Comparator switches off the Gate Driver.
Improved Current Mode
5V RFB FB C8 Soft-Start Comparator PWM-Latch
VOSC
max. Duty Cycle
PWM Comparator
0.6V
Voltage Ramp
0.6V FB
t
Optocoupler
PWM OP CS X3.2 Improved Current Mode
Gate Driver
156ns time delay
t
Figure 8
PWM Controlling
t
Figure 7 Light Load Conditions
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Functional Description 3.4 Startup Phase
Soft Start counter
Soft Start finish
SoftS
Soft Start Soft Start Soft-Start Comparator C7 & G7
V SoftS
Gate Driver
V SoftS2 V SoftS1
Figure 10
0.6V x3.2 PWM OP CS
Soft Start Phase
5V R SoftS SoftS
Figure 9
Soft Start
In the Startup Phase, the IC provides a Soft Start period to control the maximum primary current by means of a duty cycle limitation. The Soft Start function is a built-in function and it is controlled by an internal counter. When the VVCC exceeds the on-threshold voltage, the IC starts the Soft Start mode. The function is realized by an internal Soft Start resistor, a current sink and a counter. And the amplitude of the current sink is controlled by the counter.
Soft Start 32I Counter
8I
4I
2I
I
Figure 11
Soft Start Circuit
After the IC is switched on, the VSoftS voltage is controlled such that the voltage is increased stepwisely (32 steps) with the increase of the counts. The Soft Start counter would send a signal to the current sink control in every 600us such that the current sink decrease gradually and the duty ratio of the gate drive increase gradually. The Soft Start will be finished in 20ms after the IC is switched on. At the end of the Soft Start period, the current sink is switched off.
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Functional Description
The Start-Up time tStart-Up before the converter output voltage VOUT is settled, must be shorter than the SoftStart Phase tSoft-Start (see Figure 13). By means of Soft-Start there is an effective minimization of current and voltage stresses on the integrated CoolMOS(R), the clamp circuit and the output overshoot and it helps to prevent saturation of the transformer during Start-Up.
VSoftS
VSOFTS32
tSoft-Start
3.5
Gate Driver t
PWM Section
0.75 Oscillator Duty Cycle max Clock PWM Section
t
Figure 12 Gate drive signal under Soft-Start Phase
Frequency Jitter
Within the soft start period, the duty cycle is increasing from zero to maximum gradually (see Figure 12). In addition to Start-Up, Soft-Start is also activated at each restart attempt during Auto Restart.
Soft Start Block Soft Start Comparator 1 G8 S R
FF1 Gate Driver Q & G9
VSoftS tSoft-Start VSOFTS32
PWM Comparator Current Limiting
CoolMOS(R) Gate
VFB 4.0V
t
Figure 14
PWM Section Block
VOUT VOUT tStart-Up
t
t
Figure 13 Start Up Phase
3.5.1 Oscillator The oscillator generates a fixed frequency of 100KHz with frequency jittering of 4% (which is 4KHz) at a jittering period of 4ms. A capacitor, a current source and a current sink which determine the frequency are integrated. The charging and discharging current of the implemented oscillator capacitor are internally trimmed, in order to achieve a very accurate switching frequency. The ratio of controlled charge to discharge current is adjusted to reach a maximum duty cycle limitation of Dmax=0.75. Once the Soft Start period is over and when the IC goes into normal operating mode, the switching frequency of the clock is varied by the control signal from the Soft Start block. Then the switching frequency is varied in range of 100KHz 4KHz at period of 4ms.
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Functional Description
3.5.2 PWM-Latch FF1 The output of the oscillator block provides continuous pulse to the PWM-Latch which turns on/off the internal CoolMOS(R) After the PWM-Latch is set, it is reset by the PWM comparator, the Soft Start comparator or the Current -Limit comparator. When it is in reset mode, the output of the driver is shut down immediately. 3.5.3 Gate Driver
Spike Blanking 190ns
VCC
is set to low in order to disable power transfer to the secondary side.
3.6
Current Limiting
PWM Latch Latched Off FF1 Mode Current Limiting 1.66V C11
PWM-Latch 1
Propagation-Delay Compensation Vcsth C10
Gate CoolMOS
(R)
PWM-OP & G10 C12 0.31V
Leading Edge Blanking 220ns
Gate Driver
Figure 15
Gate Driver
Active Burst Mode
10k D1
1pF
The driver-stage is optimized to minimize EMI and to provide high circuit efficiency. This is done by reducing the switch on slope when exceeding the internal CoolMOS(R) threshold. This is achieved by a slope control of the rising edge at the driver's output (see Figure 16).
CS
Figure 17 Current Limiting Block There is a cycle by cycle peak current limiting operation realized by the Current-Limit comparator C10. The source current of the integrated CoolMOS(R) is sensed via an external sense resistor RSense. By means of RSense the source current is transformed to a sense voltage VSense which is fed into the pin CS. If the voltage VSense exceeds the internal threshold voltage Vcsth, the comparator C10 immediately turns off the gate drive by resetting the PWM Latch FF1. A Propagation Delay Compensation is added to support the immediate shut down of the integrated CoolMOS(R) with very short propagation delay. Thus the influence of the AC input voltage on the maximum output power can be reduced to minimal. In order to prevent the current limit from distortions caused by leading edge spikes, a Leading Edge Blanking is integrated in the current sense path for the comparators C10, C12 and the PWM-OP. The output of comparator C12 is activated by the Gate G10 if Active Burst Mode is entered. When it is activated, the current limiting is reduced to 0.31V. This
(internal) VGate
ca. t = 130ns 5V
t
Figure 16 Gate Rising Slope Thus the leading switch on spike is minimized. Furthermore the driver circuit is designed to eliminate cross conduction of the output stage. During power up, when VCC is below the undervoltage lockout threshold VVCCoff, the output of the Gate Driver
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Functional Description
voltage level determines the maximum power level in Active Burst Mode. Furthermore, the comparator C11 is implemented to detect dangerous current levels which could occur if there is a short winding in the transformer or the secondary diode is shorten. To ensure that there is no accidentally entering of the Latched Mode by the comparator C11, a 190ns spike blanking time is integrated in the output path of comparator C11. 3.6.1 Leading Edge Blanking The overshoot of Signal2 is larger than of Signal1 due to the steeper rising waveform. This change in the slope is depending on the AC input voltage. Propagation Delay Compensation is integrated to reduce the overshoot due to dI/dt of the rising primary current. Thus the propagation delay time between exceeding the current sense threshold Vcsth and the switching off of the integrated internal CoolMOS(R) is compensated over temperature within a wide range. Current Limiting is then very accurate. For example, Ipeak = 0.5A with RSense = 2. The current sense threshold is set to a static voltage level Vcsth=1V without Propagation Delay Compensation. A current ramp of dI/dt = 0.4A/s, or dVSense/dt = 0.8V/s, and a propagation delay time of tPropagation Delay =180ns leads to an Ipeak overshoot of 14.4%. With the propagation delay compensation, the overshoot is only around 2% (see Figure 20).
with compensation without compensation
VSense
Vcsth tLEB = 220ns
V
1,3
t
VSense
Figure 18 Leading Edge Blanking Whenever the internal CoolMOS(R) is switched on, a leading edge spike is generated due to the primaryside capacitances and reverse recovery time of the secondary-side rectifier. This spike can cause the gate drive to switch off unintentionally. In order to avoid a premature termination of the switching pulse, this spike is blanked out with a time constant of tLEB = 220ns.
1,25 1,2 1,15 1,1 1,05 1 0,95 0,9 0 0,2 0,4 0,6 0,8 1 1,2 1,4 1,6 1,8 2
V
dVSense dt
s
3.6.2
Propagation Delay Compensation
Figure 20
Overcurrent Shutdown
In case of overcurrent detection, there is always propagation delay to switch off the internal CoolMOS(R). An overshoot of the peak current Ipeak is induced to the delay, which depends on the ratio of dI/dt of the peak current (see Figure 19).
The Propagation Delay Compensation is realized by means of a dynamic threshold voltage Vcsth (see Figure 21). In case of a steeper slope the switch off of the driver is earlier to compensate the delay.
V OSC
m a x. D uty C ycle
Signal2 ISense Ipeak2 Ipeak1 ILimit IOvershoot2
Signal1 tPropagation Delay
o ff tim e
V S e n se
P ro p ag a tio n D e la y
t
IOvershoot1
V csth
t
Figure 19 Current Limiting Figure 21
S ig n a l1
S ig n a l2
t
Dynamic Voltage Threshold Vcsth
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Functional Description 3.7 Control Unit
the 8.0us spike blanking time, the Auto Restart Mode is activated. For example, if CBK = 0.22uF, IBK = 8.4uA Blanking time = 20ms + CBK x (4.0 - 0.9) / IBK = 100ms The 20ms blanking time circuit after C4 is disabled by the soft stat block such that the controller can start up properly. The Active Burst Mode has basic blanking mode only while the Auto Restart Mode has both the basic and the extendable blanking mode. 3.7.2 Active Burst Mode The IC enters Active Burst Mode under low load conditions. With the Active Burst Mode, the efficiency increases significantly at light load conditions while still maintaining a low ripple on VOUT and a fast response on load jumps. During Active Burst Mode, the IC is controlled by the FB signal. Since the IC is always active, it can be a very fast response to the quick change at the FB signal. The Start up Cell is kept OFF in order to minimize the power loss.
The Control Unit contains the functions for Active Burst Mode, Auto Restart Mode and Latched Off Mode. The Active Burst Mode and the Auto Restart Mode both have 20ms internal Blanking Time. For the Auto Restart Mode, a further extendable Blanking Time is achieved by adding external capacitor at BL pin. By means of this Blanking Time, the IC avoids entering into these two modes accidentally. Furthermore those buffer time for the overload detection is very useful for the application that works in low current but requires a short duration of high current occasionally. 3.7.1 Basic and Extendable Blanking Mode
BL # CBK
IBK
5.0V
0.9V 1 S1 G2
Soft Start block
Internal Bias
C3 4.0V Spike Blanking 8.0us & 4.5V C4 20ms Blanking Time G5 Auto Restart Mode
20 ms Blanking Time
Current Limiting & G10
4.5V C4
FB
C5 1.35V
FB
20ms Blanking Time & G6 Active Burst Mode Control Unit
C5 1.35V
& G6
Active Burst Mode
C6a 3.61V & C6b 3.0V Control Unit G11
Figure 22
Basic and Extendable Blanking Mode
There are 2 kinds of Blanking mode; basic mode and the extendable mode. The basic mode has an internal pre-set 20ms blanking time while the extendable mode has extended blanking time to basic mode by connecting an external capacitor to the BL pin. For the extendable mode, the gate G5 is blocked even though the 20ms blanking time is reached if an external capacitor CBK is added to BL pin. While the 20ms blanking time is passed, the switch S1 is opened by G2. Then the 0.9V clamped voltage at BL pin is charged to 4.0V through the internal IBK constant current. Then G5 is enabled by comparator C3. After
Figure 23
Active Burst Mode
The Active Burst Mode is located in the Control Unit. Figure 23 shows the related components. 3.7.2.1 Entering Active Burst Mode The FB signal is kept monitoring by the comparator C4. During normal operation, the internal blanking time counter is reset to 0. When FB signal falls below 1.35V,
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Functional Description
it starts to count. When the counter reach 20ms and FB signal is still below 1.35V, the system enters the Active Burst Mode. This time window prevents a sudden entering into the Active Burst Mode due to large load jumps. After entering Active Burst Mode, a burst flag is set and the internal bias is switched off in order to reduce the current consumption of the IC to approx. 450uA. It needs the application to enforce the VCC voltage above the Undervoltage Lockout level of 10.5V such that the Startup Cell will not be switched on accidentally. Or otherwise the power loss will increase drastically. The minimum VCC level during Active Burst Mode depends on the load condition and the application. The lowest VCC level is reached at no load condition. 3.7.2.2 Working in Active Burst Mode After entering the Active Burst Mode, the FB voltage rises as VOUT starts to decrease, which is due to the inactive PWM section. The comparator C6a monitors the FB signal. If the voltage level is larger than 3.61V, the internal circuit will be activated; the Internal Bias circuit resumes and starts to provide switching pulse. In Active Burst Mode the gate G10 is released and the current limit is reduced to 0.31V. In one hand, it can reduce the conduction loss and the other hand, it can reduce the audible noise. If the load at VOUT is still kept unchanged, the FB signal will drop to 3.0V. At this level the C6b deactivates the internal circuit again by switching off the internal Bias. The gate G11 is active again as the burst flag is set after entering Active Burst Mode. In Active Burst Mode, the FB voltage is changing like a saw tooth between 3.0V and 3.61V (see Figure 24). 3.7.2.3 Leaving Active Burst Mode The FB voltage will increase immediately if there is a high load jump. This is observed by the comparator C4. As the current limit is ca. 31% during Active Burst Mode, a certain load jump is needed so that the FB signal can exceed 4.5V. At that time the comparator C4 resets the Active Burst Mode control which in turn blocks the comparator C12 by the gate G10. The maximum current can then be resumed to stabilize VOUT.
VFB
4.5V 3.61V 3.0V 1.35V Blanking Timer
Entering Active Burst Mode
Leaving Active Burst Mode
t
20ms Blanking Time
VCS
1.06V 0.31V Current limit level during Active Burst Mode
t
VVCC
t
10.5V
IVCC
2.5mA
t
450uA
VOUT
t
t
Figure 24
Signals in Active Burst Mode
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Functional Description
3.7.3 Protection Modes The IC provides several protection features which are separated into two categories. Some enter Latched Off Mode and the others enter Auto Restart Mode. Besides the pre-defined protection feature for the Latch off mode, there is also an external Latch off Enable pin for customer defined Latch off protection features. The Latched Off Mode can only be reset if VCC falls below 6.23V. Both modes prevent the SMPS from destructive states.The following table shows the relationship between possible system failures and the chosen protection modes. VCC Overvoltage Overtemperature External latch enable Overload Open Loop VCC Undervoltage Short Optocoupler 3.7.3.1 Latched Off Mode Latched Off Mode Latched Off Mode Auto Restart Mode Auto Restart Mode Auto Restart Mode Auto Restart Mode The VCC voltage is observed by comparator C1 while the FB voltage is monitored by the comparator C4. If the VCC voltage is > 24V and the FB is > 4.5V, the overvoltage detection is activated. That means the overvoltage detection is only activated if the FB signal is outside the operating range > 4.5V, e.g. when Open Loop happens. The logic can eliminate the possible of entering Latch off mode if there is a small voltage overshoots of VVCC during normal operating. The internal Voltage Reference is switched off most of the time once Latched Off Mode is entered in order to minimize the current consumption of the IC. This Latched Off Mode can only be reset if the VVCC < 6.23V. In this mode, only the UVLO is working which controls the Startup Cell by switching on/off at VVCCon/VVCCoff. During this phase, the average current consumption is only 250A. As there is no longer a self-supply by the auxiliary winding, the VCC drops. The Undervoltage Lockout switches on the integrated Startup Cell when VCC falls below 10.5V. The Startup Cell is switched off again when VCC has exceeded 18V. Once the Latched Off Mode was entered, there is no Start Up Phase whenever the VCC exceeds the switch-on level of the Undervoltage Lockout. Therefore the VCC voltage changes between the switch-on and switch-off levels of the Undervoltage Lockout with a saw tooth shape (see Figure 26).
Short Winding/Short Diode Latched Off Mode
Latched Off Mode
CS
1.66V C11
VVCC
Spike Blanking 190ns Latched Off Mode Reset VVCC < 6.23V
18V
UVLO 1ms counter
1 G3 Latched Off Mode
10.5V
BL TLE
# Latch Enable signal 0.1V C2
IVCCStart
8us Blanking Time
t
0.9mA
VCC C1 24V
& G1
Spike Blanking 8.0us
VOUT
Figure 26 Signals in Latched Off Mode
t
4.5V C4
FB
Thermal Shutdown Tj >140C Control Unit
Voltage Reference
Figure 25
Latched Off Mode
The Thermal Shutdown block monitors the junction temperature of the IC. After detecting a junction temperature higher than latched thermal shutdown temperature; TjSD, the Latched Off Mode is entered. The signals coming from the temperature detection and VCC overvoltage detection are fed into a spike blanking with a time constant of 8.0s in order to ensure the system reliability.
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Furthermore, a short winding or short diode on the secondary side can be detected by the comparator C11 which is in parallel to the propagation delay compensated current limit comparator C10. In normal operating mode, comparator C10 controls the maximum level of the CS signal at 1.06V. If there is a failure such as short winding or short diode, C10 is no longer able to limit the CS signal at 1.06V. Instead the comparator C11 detects the peak current voltage > 1.66V and enters the Latched Off Mode immediately in order to keep the SMPS in a safe stage. In case the pre-defined Latch Off features are not sufficient, there is a customer defined external Latch Enable feature. The Latch Off Mode can be triggered by pulling down the BL pin to < 0.1V. It can simply add a trigger signal to the base of the externally added transistor, TLE at the BL pin. To ensure this latch function will not be mis-triggered during start up, a 1ms delay time is implemented to blank the unstable signal. 3.7.3.2 Auto Restart Mode to charge the capacitor CBK from 0.9V to 4.0V after the switch S1 is released. The charging time from 0.9V to 4.0V are the extendable blanking time. If CBK is 0.22uF and IBK is 8.4uA, the extendable blanking time is around 80ms and the total blanking time is 100ms. In combining the FB and blanking time, there is a blanking window generated which prevents the system to enter Auto Restart Mode due to large load jumps. In case of VCC undervoltage, the IC enters into the Auto Restart Mode and starts a new startup cycle. Short Optocoupler also leads to VCC undervoltage as there is no self supply after activating the internal reference and bias. In contrast to the Latched Off Mode, there is always a Startup Phase with switching cycles in Auto Restart Mode. After this Start Up Phase, the conditions are again checked whether the failure mode is still present. Normal operation is resumed once the failure mode is removed that had caused the Auto Restart Mode.
BL
#
5.0V IBK
CBK
0.9V 1 S1 G2
C3 4.0V
Spike Blanking 8.0us &
4.5V
FB
C4
20ms Blanking Time
G5
Auto Restart Mode Control Unit
Figure 27
Auto Restart Mode
In case of Overload or Open Loop, the FB exceeds 4.5V which will be observed by comparator C4. Then the internal blanking counter starts to count. When it reaches 20ms, the switch S1 is released. Then the clamped voltage 0.9V at VBL can increase. When there is no external capacitor CBK connected, the VBL will reach 4.0V immediately. When both the input signals at AND gate G5 is positive, the Auto-Restart Mode will be activated after the extra spike blanking time of 8.0us is elapsed. However, when an extra blanking time is needed, it can be achieved by adding an external capacitor, CBK. A constant current source of IBK will start
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Electrical Characteristics
4
Note:
Electrical Characteristics
All voltages are measured with respect to ground (Pin 8). The voltage levels are valid if other ratings are not violated.
4.1
Note:
Absolute Maximum Ratings
Absolute maximum ratings are defined as ratings, which when being exceeded may lead to destruction of the integrated circuit. For the same reason make sure, that any capacitor that will be connected to pin 7 (VCC) is discharged before assembling the application circuit.Ta=25C unless otherwise specified.
Parameter Drain Source Voltage Pulse drain current, tp limited by max. Tj=150C
Symbol VDS ID_Puls -
Limit Values min. max. 650 3.4 0.07 1.0 27 5.5 5.5 5.5 150 150 90 260 22)
Unit V A mJ A V V V V C C K/W C kV
Remarks Tj=110C
Avalanche energy, repetitive tAR limited EAR by max. Tj=150C1) Avalanche current, repetitive tAR limited IAR by max. Tj=150C VCC Supply Voltage FB Voltage BL Voltage CS Voltage Junction Temperature Storage Temperature Thermal Resistance Junction -Ambient Soldering temperature, wavesoldering only allowed at leads ESD Capability (incl. Drain Pin)
1) 2) 3)
VVCC VFB VFB VCS Tj TS RthJA Tsold VESD
-0.3 -0.3 -0.3 -0.3 -40 -55 -
Controller & CoolMOS(R) PG-DIP-8 1.6mm (0.063in.) from case for 10s Human body model3)
Repetitive avalanche causes additional power losses that can be calculated as PAV=EAR*f 2KV is for all pin combinations except VCC to GND is 1KV According to EIA/JESD22-A114-B (discharging a 100pF capacitor through a 1.5k series resistor)
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Electrical Characteristics 4.2
Note:
Operating Range
Within the operating range the IC operates as described in the functional description. Symbol VVCC TjCon TjCoolMOS Limit Values min. max. 26 130 150 V C C Max value limited due to thermal shut down of controller VVCCoff -25 -25 Unit Remarks
Parameter VCC Supply Voltage Junction Temperature of Controller Junction Temperature of CoolMOS(R)
4.3
4.3.1 Note:
Characteristics
Supply Section The electrical characteristics involve the spread of values within the specified supply voltage and junction temperature range TJ from - 25 C to 130 C. Typical values represent the median values, which are related to 25C. If not otherwise stated, a supply voltage of VCC = 18 V is assumed. Symbol min. IVCCstart IVCCcharge1 IVCCcharge2 IVCCcharge3 0.55 Limit Values typ. 150 0.90 0.7 0.2 1.5 2.5 250 250 max. 250 5.0 1.60 50 2.5 4.2 A mA mA mA A mA mA A A IFB = 0A IFB = 0A IFB = 0A VVCC =17V VVCC = 0V VVCC = 1V VVCC =17V VDrain = 450V at Tj=100C Unit Test Condition
Parameter Start Up Current VCC Charge Current
Leakage Current of Start Up Cell and CoolMOS(R) Supply Current with Inactive Gate Supply Current with Active Gate Supply Current in Latched Off Mode Supply Current in Auto Restart Mode with Inactive Gate Supply Current in Active Burst Mode with Inactive Gate VCC Turn-On Threshold VCC Turn-Off Threshold VCC Turn-On/Off Hysteresis
IStartLeak IVCCsup1 IVCCsup2 IVCClatch IVCCrestart
IVCCburst1 IVCCburst2 VVCCon VVCCoff VVCChys
17.0 9.8 -
450 450 18.0 10.5 7.5
950 950 19.0 11.2 -
A A V V V
VFB = 2.5V VVCC = 11.5V,VFB = 2.5V
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4.3.2 Internal Voltage Reference Symbol min. Trimmed Reference Voltage VREF 4.90 Limit Values typ. 5.00 max. 5.10 V measured at pin FB IFB = 0 Unit Test Condition
Parameter
4.3.3 Parameter
PWM Section Symbol min. fOSC1 fOSC2 fjitter Dmax Dmin AV VOffset-Ramp 87 92 0.70 0 3.0 9 Limit Values typ. 100 100 4.0 0.75 3.2 0.6 0.5 15.4 max. 113 108 0.80 3.4 4.3 22 V V V k CS=1V, limited by Comparator C41) VFB < 0.3V kHz kHz kHz Tj = 25C Tj = 25C Unit Test Condition
Fixed Oscillator Frequency Frequency Jittering Range Max. Duty Cycle Min. Duty Cycle PWM-OP Gain Voltage Ramp Offset
VFB Operating Range Min Level VFBmin VFB Operating Range Max level FB Pull-Up Resistor
1)
VFBmax RFB
The parameter is not subjected to production test - verified by design/characterization
4.3.4
Soft Start time Symbol min. tSS Limit Values typ. 20.0 max. ms Unit Test Condition
Parameter Soft Start time
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Electrical Characteristics
4.3.5 Parameter Clamped VBL voltage during Normal Operating Mode Blanking time voltage limit for Comparator C3 Over Load & Open Loop Detection Limit for Comparator C4 Active Burst Mode Level for Comparator C5 Active Burst Mode Level for Comparator C6a Active Burst Mode Level for Comparator C6b Overvoltage Detection Limit Latch Enable level at BL pin Charging current at BL pin Control Unit Symbol min. VBLclmp VBKC3 VFBC4 VFBC5 VFBC6a VFBC6b VVCCOVP VLE IBK 0.85 3.85 4.28 1.23 3.48 2.88 23 0.07 5.8 Limit Values typ. 0.90 4.00 4.50 1.35 3.61 3.00 24 0.1 8.4 max. 0.95 4.15 4.72 1.43 3.76 3.12 25 0.2 10.9 V V V V V V V V A After Active Burst Mode is entered After Active Burst Mode is entered VFB = 5V > 30s Charge starts after the built-in 20ms blanking time elapsed VFB = 4V Unit Test Condition
Latched Thermal Shutdown1) Built-in Blanking Time for Overload Protection or enter Active Burst Mode Inhibit Time for Latch Enable function during Start up Spike Blanking Time before Latch off
or Auto Restart Protection
TjSD tBK
130 -
140 20
150 -
C ms without external capacitor at BL pin Count when VCC > 18V
tIHLE tSpike VVCCPD
5.2
1.0 8.0 6.23
7.8
ms s V
Power Down Reset for Latched Mode
1)
After Latched Off Mode is entered
The parameter is not subjected to production test - verified by design/characterization. The thermal shut down temperature refers to the junction temperature of the controller. The trend of all the voltage levels in the Control Unit is the same regarding the deviation except VVCCOVP and VVCCPD
Note:
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Electrical Characteristics
4.3.6 Parameter Peak Current Limitation (incl. Propagation Delay) Peak Current Limitation during Active Burst Mode Leading Edge Blanking CS Input Bias Current Over Current Detection for Latched Off Mode CS Spike Blanking for Comparator C11 4.3.7 CoolMOS(R) Section Current Limiting Symbol min. Vcsth VCS2 tLEB ICSbias VCS1 tCSspike 0.99 0.27 -1.5 1.57 Limit Values typ. 1.06 0.31 220 -0.2 1.66 190 max. 1.09 0.37 1.76 V V ns A V ns VCS =0V dVsense / dt = 0.6V/s (see Figure 20) Unit Test Condition
Parameter Drain Source Breakdown Voltage Drain Source On-Resistance
Symbol min. V(BR)DSS RDSon 600 650 -
Limit Values typ. 2.95 6.60 7.0 302) 302) max. 3.42 7.56 -
Unit V V pF ns ns
Test Condition Tj = 25C Tj = 110C Tj = 25C Tj=125C1) at ID = 1.0A VDS = 0V to 480V
Effective output capacitance, energy related Rise Time Fall Time
1) 2)
Co(er) trise tfall
The parameter is not subjected to production test - verified by design/characterization Measured in a Typical Flyback Converter Application
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Temperature derating curve
5
Temperature derating curve
Safe Operating Area for ICE3A(B)1065(ELJ) ID = f ( VDS ) parameter : D = 0, TC = 25deg.C 10
1
ID [A]
0.1
0.01
tp = tp = tp = tp = tp = DC
0.1ms 1ms 10ms 100ms 1000ms
0.001 1 10 V DS [V] 100 1000
Figure 28
Safe Operating area (SOA) curve
SOA temperature derating coefficient curve ( package dissipation ) for F3 & F2 CoolSET
120
SOA temperature derating coefficient [%]
100
80
60
40
20
0 0 20 40 60 80 100 120 140 Ambient/Case temperature Ta/Tc [deg.C] Ta : DIP, Tc : TO220
Figure 29
SOA temperature derating coefficient curve
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Outline Dimension
6
Outline Dimension
PG-DIP-8-6 / PG-DIP-8-9 (Plastic Dual In-Line Outline)
Figure 30
PG-DIP-8 (PB-free Plating Plastic Dual In-Line Outline)
Dimensions in mm
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Marking
7
Marking
Marking
Figure 31
Marking
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Schematic for recommended PCB layout
8
Schematic for recommended PCB layout
TR1
BR1 Spark Gap 3 FUSE1
R11 C11 bulk cap D11
C12
D21
L
Spark Gap 1
X-CAP C1 L1
Vo
C21
GND
Spark Gap 2 Spark Gap 4 C2 Y-CAP C3 Y-CAP C4 Y-CAP SOFTS GND C13 C14 R12 CS D11 Z11
GND
C16 R21
N
IC11
DRAIN R13 R14 VCC R23 FB C15 C23 R24 NC R22 C22 D13
F3 CoolSET
IC12
IC21 R25
F3 CoolSET schematic for recommended PCB layout
Figure 32
Schematic for recommended PCB layout
General guideline for PCB layout design using F3 CoolSET(R) (refer to Figure 32): 1. "Star Ground "at bulk capacitor ground, C11: "Star Ground "means all primary DC grounds should be connected to the ground of bulk capacitor C11 separately in one point. It can reduce the switching noise going into the sensitive pins of the CoolSET(R) device effectively. The primary DC grounds include the followings. a. DC ground of the primary auxiliary winding in power transformer, TR1, and ground of C16 and Z11. b. DC ground of the current sense resistor, R12 c. DC ground of the CoolSET(R) device, GND pin of IC11; the signal grounds from C13, C14, C15 and collector of IC12 should be connected to the GND pin of IC11 and then "star "connect to the bulk capacitor ground. d. DC ground from bridge rectifier, BR1 e. DC ground from the bridging Y-capacitor, C4 2. High voltage traces clearance: High voltage traces should keep enough spacing to the nearby traces. Otherwise, arcing would incur. a. 400V traces (positive rail of bulk capacitor C11) to nearby trace: > 2.0mm b. 600V traces (drain voltage of CoolSET(R) IC11) to nearby trace: > 2.5mm 3. Filter capacitor close to the controller ground: Filter capacitors, C13, C14 and C15 should be placed as close to the controller ground and the controller pin as possible so as to reduce the switching noise coupled into the controller. Guideline for PCB layout design when >3KV lightning surge test applied (refer to Figure 32): 1. Add spark gap Spark gap is a pair of saw-tooth like copper plate facing each other which can discharge the accumulated charge during surge test through the sharp point of the saw-tooth plate. a. Spark Gap 3 and Spark Gap 4, input common mode choke, L1: Gap separation is around 1.5mm (no safety concern)
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Schematic for recommended PCB layout
b. Spark Gap 1 and Spark Gap 2, Live / Neutral to GROUND: These 2 Spark Gaps can be used when the lightning surge requirement is >6KV. 230Vac input voltage application, the gap separation is around 5.5mm 115Vac input voltage application, the gap separation is around 3mm 2. Add Y-capacitor (C2 and C3) in the Live and Neutral to ground even though it is a 2-pin input 3. Add negative pulse clamping diode, D11 to the Current sense resistor, R12: The negative pulse clamping diode can reduce the negative pulse going into the CS pin of the CoolSET(R) and reduce the abnormal behavior of the CoolSET(R). The diode can be a fast speed diode such as IN4148. The principle behind is to drain the high surge voltage from Live/Neutral to Ground without passing through the sensitive components such as the primary controller, IC11.
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12 May 2009
Total Quality Management
Qualitat hat fur uns eine umfassende Bedeutung. Wir wollen allen Ihren Anspruchen in der bestmoglichen Weise gerecht werden. Es geht uns also nicht nur um die Produktqualitat - unsere Anstrengungen gelten gleichermaen der Lieferqualitat und Logistik, dem Service und Support sowie allen sonstigen Beratungs- und Betreuungsleistungen. Dazu gehort eine bestimmte Geisteshaltung unserer Mitarbeiter. Total Quality im Denken und Handeln gegenuber Kollegen, Lieferanten und Ihnen, unserem Kunden. Unsere Leitlinie ist jede Aufgabe mit Null Fehlern" zu losen - in offener Sichtweise auch uber den eigenen Arbeitsplatz hinaus - und uns standig zu verbessern. Unternehmensweit orientieren wir uns dabei auch an top" (Time Optimized Processes), um Ihnen durch groere Schnelligkeit den entscheidenden Wettbewerbsvorsprung zu verschaffen. Geben Sie uns die Chance, hohe Leistung durch umfassende Qualitat zu beweisen. Wir werden Sie uberzeugen. Quality takes on an allencompassing significance at Semiconductor Group. For us it means living up to each and every one of your demands in the best possible way. So we are not only concerned with product quality. We direct our efforts equally at quality of supply and logistics, service and support, as well as all the other ways in which we advise and attend to you. Part of this is the very special attitude of our staff. Total Quality in thought and deed, towards co-workers, suppliers and you, our customer. Our guideline is "do everything with zero defects", in an open manner that is demonstrated beyond your immediate workplace, and to constantly improve. Throughout the corporation we also think in terms of Time Optimized Processes (top), greater speed on our part to give you that decisive competitive edge. Give us the chance to prove the best of performance through the best of quality - you will be convinced.
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Published by Infineon Technologies AG

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